Method, system, and product for isolating memory system defects to a particular memory system component

ABSTRACT

A method, system, and product are disclosed for isolating a defect in a memory system by determining in which particular component of the memory system the defect exists. The memory system includes multiple components. The components include a physical memory module, a memory card to which the physical memory module is attached, and a memory controller for controlling the memory card. The memory card includes one or more electrical buffers for driving or detecting the memory signals. The buffers may be used as virtual memory elements. Each component is tested separately in order to identify the defective component with the help of virtual memory system elements. The components are tested by first testing the physical memory module. If the physical memory module passes the test, the memory card is then tested. If the memory card passes its test, the memory controller is tested.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to the field of data processingsystems, and more specifically to a method, system, and computer programproduct for testing a memory system. Still more particularly, thepresent invention relates to a method, system, and computer programproduct for isolating a defect in a memory system by determining inwhich particular component of the memory system the defect exists.

2. Description of Related Art

Currently, in a minimum system configuration with a single memoryextent, there is no reliable method in computer memory fault isolationtechniques to isolate a hardware problem among a memory module, such asa dual inline memory module (DIMM), a memory controller, and a memorycard, which is the device to which memory modules are attached. Theknown methods test all parts of the memory system coupled together. Withall parts of the memory system coupled together, patterns of data arewritten using the data and address bits to the memory subsystem usingthe memory controller. Data is then read back from the memory subsystemusing the memory controller. First the memory controller is tested. Thelogic around memory controller is then tested. The logic for memory cardis tested next, and finally memory modules are tested. The patternwritten to the memory system is then compared to the pattern read backfrom the memory system. If the patterns do not match, then it isdetermined that a defect exists within the memory system. However, allcomponents of memory systems are tested as one single unit and cannot betested individually. In addition to that, in the minimum configuration,when only one of each memory system component, such as memorycontroller, memory card, and memory module, is present any detectederror may reside in any one of the interconnected elements and cannot beisolated.

This prior art method for determining if a defect exists in the memorysystem cannot test various components of memory system individuallybecause the three components, the memory controller, memory card, andmemory modules, are all tested together as a coupled unit. Further, inthe case of the minimum configuration, the prior art method makes itdifficult to identify exact which component is defective. Further tothat, the prior art method also does not elaborately test the memorycard component of memory system and the logic around it. As a result, inthe case of a defective memory card component, the problem cannot beisolated to the defective memory component and may increase the numberof field replacement units in order to correct the memory system errors.

Therefore, a need exists for a method, system, and product for isolatinga defect in a memory system by determining in which particular componentof the memory system the defect exists regardless of the systemconfiguration and also provide the ability to test various memory systemcomponents individually without having a dependency among each other.

SUMMARY OF THE INVENTION

A method, system, and product are disclosed for isolating a defect in amemory system by determining in which particular component of the memorysystem the defect exists. The memory system includes multiplecomponents. The components include one or more physical memory module,one or more memory card to which physical memory modules are attached,and one or more memory controller for controlling the memory card. Thememory card includes one or more electrical buffers for driving ordetecting the memory signals. The buffers may be used as virtual memorysystem elements in accordance with the method described in thisinvention. Each memory component is tested separately in order toidentify the defective component. The memory system is tested by firsttesting the physical memory modules using the electrical buffers as avirtual memory controller. If the physical memory modules pass the test,the memory card is then tested using the electrical buffers acting asvirtual memory modules. If the memory card passes its test, the memorycontroller is tested using any of the prior art methods. In this manner,a defect may be isolated to a physical memory module, the memory card,or the memory controller.

The above as well as additional objectives, features, and advantages ofthe present invention will become apparent in the following detailedwritten description.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objectives and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 depicts a pictorial representation of a network of dataprocessing systems in which the present invention may be implemented inaccordance with the present invention;

FIG. 2 is a detailed block diagram of a data processing system in whichthe present invention may be implemented in accordance with the presentinvention;

FIG. 3A is a block diagram of a memory subsystem that includes a memorycard, physical memory modules, and buffers in accordance with thepresent invention;

FIG. 3B is a block diagram of a memory subsystem that includes a memorycard, physical memory modules, and tristate devices in accordance withthe present invention;

FIG. 4 depicts a high level flow chart which illustrates testing amemory system, by first testing physical memory modules and then othermemory system components in accordance with the present invention;

FIG. 5 depicts a high level flow chart which illustrates testing othermemory system components such as memory card and memory controller inaccordance with the present invention;

FIG. 6 depicts a high level flow chart which illustrates testingphysical memory modules (physical DIMMs) in accordance with the presentinvention;

FIG. 7 depicts a high level flow chart which illustrates testing amemory card in accordance with the present invention; and

FIG. 8 depicts a high level flow chart which illustrates testing amemory controller using any of the prior art methods in accordance withthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the present invention and its advantages arebetter understood by referring to the figures, like numerals being usedfor like and corresponding parts of the accompanying figures.

The present invention is a method, system, and computer program productfor isolating a defect in a memory system by determining in whichcomponent of the memory system the defect exists, regardless of thesystem configuration, by testing each memory system componentindividually. The present invention reduces the number of fieldreplacement units that must be carried by service persons by isolating adefect to a specific component of the memory system. In this manner,prior to calling a service person, the defective component isidentified. Therefore, when a defect occurs, a call may be made to theservice person, and the call may include an identification of theparticular component of the memory system that is defective and thatneeds to be replaced. Thus, the defective device is identified prior tomaking a service call.

The present invention isolates defects to a particular component bytesting each memory system component individually in a particular order.First, the physical memory modules are tested. Next, the memory card andthen the memory controller are tested.

First, the physical memory modules attached to the memory cardthemselves are tested. A test pattern is setup to test the physicalmemory modules. A memory card typically includes electrical buffers aspart of the card. According to the present invention, while testingphysical memory modules attached to a memory card, these electricalbuffers of the memory card act as a virtual memory controller. Thesebuffers are coupled to a processor, such as a service processor,utilizing a bus, such as a JTAG bus. A test pattern is written to andthen read back from the physical memory modules utilizing the buffers asa virtual memory controller over the JTAG bus by the service processor.In this way, the physical memory modules (physical DIMMs) of the memorysystem are tested. If no error is located in any of the physical memorymodules, the present invention describes testing the memory card next.

As described, memory cards typically include electrical buffers as partof the card. According to the present invention, these buffers aretreated as virtual memory modules in order to test the memory card.These buffers are coupled to a processor, such as a service processor,utilizing a bus, such as a JTAG bus. Each buffer is then assigned aunique identifier so that the buffer may be addressed by the serviceprocessor. Each buffer is then treated by the service processor as avirtual memory module and a test is executed for the memory card and thelogic associated with the memory card. The system processor writes atest pattern to these electrical buffers. The service processor teststhe data bits by reading data patterns to a single memory locationfalling within the range of the electrical buffer which is being treatedas a virtual memory module. If the pattern that is read back matches thepattern that was written for each memory location in a virtual memorymodule, address bit verification is performed for the memory card.

Address bit verification is more complex than data bit verification. Totest address bits, the memory locations in an electrical buffer which isbeing treated as a virtual memory module are cleared to a known state,such as all zeros. Next, a known data pattern is written to a specificmemory location that falls within the range of a specified buffer orvirtual memory module. Then a specific set of addresses falling with therange of the same electrical buffer or virtual memory module is readfrom to determine if the known data pattern is read back from memorylocations other than the first specific memory location. If the knowndata pattern is read back from only the first specific memory locationand no other locations, the service processor determines that the memorycard passed the test. If the memory card passes this test, the knowndata pattern is removed from the first specific memory location and thenwritten to a next specific memory location. This process is repeateduntil all of the memory address bits are verified.

The service processor tests the memory card using the buffers as virtualmemory modules. Thus, the data and address tests described above areexecuted using the buffers to store the data patterns. When no error wasdetected in the physical memory modules testing, if an error occursduring the test of memory card using the buffers as virtual memorymodules, it is determined that the memory card is defective andisolated.

If no errors occur during the test of the memory card using the buffersas virtual memory modules, then at this time, the physical memorymodules and memory card are determined not to be defective. Next, thememory controller and support logic are tested using prior art methodssuch as Built In Self Test (BIST) or JTAG scan chain signatureverification. If an error is found in this phase, the memory controlleris identified as being defective. If no errors were detected in thememory controller test then the memory system is declared to be good.

FIG. 1 depicts a pictorial representation of a network 100 of dataprocessing systems in which the present invention may be implemented.Network data processing system 100 contains a network 102, which is themedium used to provide communications links between various devices andcomputers connected together within network data processing system 100.Network 102 may include connections, such as wire, wirelesscommunication links, or fiber optic cables.

In the depicted example, a server 104 is connected to network 102 alongwith storage unit 106. In addition, clients 108, 110, and 112 also areconnected to network 102 through a network communications device.Network 102 may include permanent connections, such as wire or fiberoptic cables, or temporary connections made through telephoneconnections. The communications network 102 also can include otherpublic and/or private wide area networks, local area networks, wirelessnetworks, data communication networks or connections, intranets,routers, satellite links, microwave links, cellular or telephonenetworks, radio links, fiber optic transmission lines, ISDN lines, Tilines, DSL, etc. In some embodiments, a user device may be connecteddirectly to a server 104 without departing from the scope of the presentinvention. Moreover, as used herein, communications include thoseenabled by wired or wireless technology.

Clients 108, 110, and 112 may be, for example, personal computers,portable computers, mobile or fixed user stations, workstations, networkterminals or servers, cellular telephones, kiosks, dumb terminals,personal digital assistants, two-way pagers, smart phones, informationappliances, or network computers. For purposes of this application, anetwork computer is any computer, coupled to a network, which receives aprogram or other application from another computer coupled to thenetwork.

In the depicted example, server 104 provides data, such as boot files,operating system images, and applications to clients 108-112. Clients108, 110, and 112 are clients to server 104. Network data processingsystem 100 may include additional servers, clients, and other devicesnot shown. FIG. 1 is intended as an example, and not as an architecturallimitation for the present invention.

FIG. 2 illustrates a detailed block diagram of a data processing systemin which the present invention may be implemented. Data processingsystem 200 may be a symmetric multiprocessor (SMP) system including aplurality of processors 201, 202, 203, and 204 connected to system bus206. For example, data processing system 200 may be an IBM RS/6000, aproduct of International Business Machines Corporation in Armonk, N. Y.,implemented as a server within a network. Alternatively, a singleprocessor system may be employed. Also connected to system bus 206 ismemory controller/cache 208, which provides an interface to a pluralityof memory subsystems 260-263. I/O bus bridge 210 is connected to systembus 206 and provides an interface to I/O bus 212. Memorycontroller/cache 208 and I/O bus bridge 210 may be integrated asdepicted.

As used herein, a memory subsystem includes a memory card to which areattached physical memory modules such as DIMMs. A memory card alsoincludes one or more buffers as described herein which may act asvirtual DIMMs. Each buffer is assigned a unique identifier and iscoupled to the data and address buses of the memory card. Each buffer isalso coupled to a processor, such as service processor 235, utilizing abus, such as JTAG bus 234. In this manner, service processor 235 maycontrol the buffers and may write data to and read data from thebuffers.

Data processing system 200 may be a logically partitioned dataprocessing system. Thus, data processing system 200 may have multipleheterogeneous operating systems (or multiple instances of a singleoperating system) running simultaneously. Each of these multipleoperating systems may have any number of software programs executingwithin it. Data processing system 200 may be logically partitioned suchthat different I/O adapters 220-221, 228-229, 236, and 248-249 may beassigned to different logical partitions.

Peripheral component interconnect (PCI) Host bridge 214 connected to I/Obus 212 provides an interface to PCI local bus 215. A number ofInput/Output adapters 220-221 may be connected to PCI bus 215 throughPCI to PCI bridge 216. Typical PCI bus implementations will supportbetween four and eight I/O adapters (i.e. expansion slots for add-inconnectors). Each I/O Adapter 220-221 provides an interface between dataprocessing system 200 and input/output devices such as, for example,other network computers, which are clients to data processing system200.

An additional PCI host bridge 222 provides an interface for anadditional PCI bus 223. PCI bus 223 is connected to a plurality of PCII/O adapters 228-229 by a PCI bus 226-227. Thus, additional I/O devices,such as, for example, modems or network adapters may be supportedthrough each of PCI I/O adapters 228-229. In this manner, dataprocessing system 200 allows connections to multiple network computers.

A memory mapped graphics adapter 248 may be connected to I/O bus 212through PCI Host Bridge 240 and PCI-PCI bridge 242 via PCI buses 244 and245 as depicted. Also, a hard disk 250 may also be connected to I/O bus212 through PCI Host Bridge 240 and PCI-PCI bridge 242 via PCI buses 241and 245 as depicted.

A PCI host bridge 230 provides an interface for a PCI bus 231 to connectto I/O bus 212. PCI bus 231 connects PCI host bridge 230 to the serviceprocessor mailbox interface and ISA bus accesses pass-through logic 294and PCI-PCI bridge 232. The ISA bus accesses pass-through logic 294 andforwards PCI accesses destined to the PCI/ISA bridge 293. The NVRAMstorage is connected to the ISA bus 296. The service processor 235 iscoupled to the service processor mailbox interface 294 through its localPCI bus 295. Service processor 235 is also connected to processors201-204 via a plurality of JTAG/I²C buses 234. JTAG/I²C buses 234 are acombination of JTAG/scan busses (see IEEE 1149.1) and Phillips I²Cbusses. However, alternatively, JTAG/ ²C buses 234 may be replaced byonly Phillips I²C busses or only JTAG/scan busses. All SP-ATTN signalsof the host processors 201, 202, 203, and 204 are connected together toan interrupt input signal of the service processor. The serviceprocessor 235 has its own local memory 291, and has access to thehardware operator control panel 290.

When data processing system 200 is initially powered up, serviceprocessor 235 uses the JTAG/scan buses 234 to interrogate the system(Host) processors 201-204, memory controller 208, and I/O bridge 210. Atcompletion of this step, service processor 235 has an inventory andtopology understanding of data processing system 200. Service processor235 also executes Built-In-Self-Tests (BISTs), Basic Assurance Tests(BATs), and memory tests on all elements found by interrogating thesystem processors 201-204, memory controller 208, and I/O bridge 210.Any error information for failures detected during the BISTs, BATs, andmemory tests are gathered and reported by service processor 235.

The JTAG bus may be extended to one or all memory subsystems, such asmemory subsystems 260-263, and to memory controller 208.

Those of ordinary skill in the art will appreciate that the hardwaredepicted in FIG. 2 may vary. For example, other peripheral devices, suchas optical disk drives and the like, also may be used in addition to orin place of the hardware depicted. The depicted example is not meant toimply architectural limitations with respect to the present invention.

FIG. 3A is a block diagram of a memory subsystem that includes a memorycard, physical memory modules, and buffers in accordance with thepresent invention. The memory card 300 a includes one or more physicalmemory modules, such as memory modules 302 and 304. Memory card 300 amay include additional empty slots 306 and 308 for attaching additionalphysical memory modules to memory card 300 a.

Typical memory cards also include one or more buffers, such as buffers310 and 312. According to the present invention buffers 310 and 312 arecoupled to a bus, such as JTAG bus 322, for communicating with aprocessor, such as service processor 235. Buffers may be written to andread from using data/address bus 318. Memory modules 302 and 304 are onthe buffered data/address bus 319 which goes into buffers 310 and 312.

Testing a memory system utilizing the existing electrical buffers 310and 312 on the memory card as virtual memory elements, such as a virtualmemory controller, permits testing the memory system utilizing hardwarethat is already present on the card with minimal modifications. Thebuffers are modified, if necessary, to couple them to a bus such as theJTAG bus.

FIG. 3B is a block diagram of a memory subsystem that includes a memorycard, physical memory modules, and tristate devices in accordance withthe present invention. A memory system may also be tested using tristatedevices 314 and 316. Typical memory cards do not include tristatedevices. Therefore, these devices may be added to a memory card. Aprocessor may control devices 314 and 316 using a bus, such as I²C bus320. Each of devices 314 and 316 includes a parallel to serial registerconversion function. There would be as many input lines on the parallelto serial register as there are address and data lines on the memorycard. These tristate devices 314 and 316 are used in the same manner asthe electrical buffers to test a memory system. Using tristate devicesto conduct the test will require additional hardware to be added to thememory card.

FIG. 4 depicts a high level flow chart which illustrates testing amemory system in accordance with the present invention. The processstarts as depicted by block 400 and thereafter passes to block 402 whichillustrates testing each physical memory module (DIMM) of the memorysystem first. The process of testing physical memory modules inaccordance with the present invention is depicted in more detail by FIG.6.

Referring again to the present invention, the process passes to block404 which illustrates a determination of whether or not an error wasdetected in one or more physical memory modules. If a determination ismade an error was detected in one or more physical memory modules, theprocess passes to block 406 which illustrates identifying the defectiveone or more physical memory modules. Thereafter, block 408 depictslogging the error(s) for the physical memory module(s) with theappropriate location code. Referring again to block 404, if adetermination is made that no error was detected in any of the physicalmodules, the process passes to block 410 which illustrates testing othermemory system components such as the memory card and the memorycontroller. The process of block 410 is depicted in more detail by FIG.5.

FIG. 5 illustrates a high level flow chart which depicts testing othermemory system components in accordance with the present invention. Theprocess starts as depicted by block 500 which illustrates starting atest for other memory system components such as a memory card and amemory controller. If the entire memory system includes more than onesuch memory component, the process illustrated by FIG. 5 is repeated foreach component.

The process then passes to block 502 which depicts testing a memory cardusing electrical buffers that are already included as part of a typicalmemory card. These buffers are used as virtual memory modules.Alternatively, the memory card may be tested utilizing tristate devicesthat have been added to the memory card. A more detailed description ofthe memory card testing process is described with reference to FIG. 7.

Thereafter, block 504 illustrates a determination of whether or not anerror was detected in the memory card. If a determination is made thatan error was detected, the process passes to block 506 which depictslogging the error(s) for the memory card with the appropriate locationcode. Referring again to block 504, if a determination is made that noerror was detected in the memory card, the process passes to block 508which illustrates testing the memory controller using a prior artmethod. A more detailed description of the memory controller testingprocess is described with reference to FIG. 8.

Referring again to the present invention, block 510, then, depicts adetermination of whether or not an error was detected in the memorycontroller. If a determination is made that an error was detected in thememory controller, the process passes to block 512 which illustrateslogging the error(s) for the memory controller with the appropriatelocation code. Referring again to block 510, if a determination is madethat no error was detected, the process terminates as depicted by block514.

FIG. 6 depicts a high level flow chart which illustrates testing aphysical memory module in accordance with the present invention. Ifthere are multiple physical memory modules (DIMMs) in the system, thisprocess is repeated for each module. The process for testing physicalmemory modules starts as depicted by block 600. Physical memory modulesare accessed via the memory card electrical buffers using the JTAG bus.Thus, the buffers are treated as a virtual memory controller. A testpattern is setup to test the physical memory modules. Next, block 602depicts scanning data and address information to these buffers. Block604, then, depicts toggling control via JTAG scan to write data tophysical memory modules using the buffers. Next, block 606 depictsrepeating the same process for other addresses within the physicalmemory module. Block 608 illustrates a determination of whether or notall addresses within the physical memory module have been written to. Ifa determination is made that there are additional addresses to write to,the process passes back to block 602. Referring again to block 608, ifdata has been written to all addresses, the process passes to block 610.

Block 610 depicts scanning address information to the physical memorymodules. Thereafter, block 612 illustrates toggling control via JTAGscan to read data from the physical memory modules. Next, block 614depicts scanning the physical memory module data from the buffers. Block616, then, illustrates a verification of the data pattern to ensure thatwhat was written is read back. Next, block 618 illustrates adetermination of whether all the memory locations were verified. If not,the process passes back to block 610. If all the memory locations wereverified, then the process terminates as depicted by block 620. Asdescribed above, tristate devices may be used instead of the buffers totest the physical memory modules.

FIG. 7 depicts a high level flow chart which illustrates testing amemory card in accordance with the present invention. The process fortesting a memory card starts as depicted by block 700. Next, block 702depicts setting up a test pattern to test a memory card. The processthen passes to block 704 which illustrates assigning a unique identifierto each buffer. Next, block 706 depicts treating electrical buffers onthe memory card as virtual memory modules. Next, block 708 depicts thesystem processor writing data and address information directly to eachbuffer by writing data and address bits to the memory subsystem. Block710, then, illustrates the service processor reading the data andaddress information back directly from the buffers using the JTAG bus.The process then terminates as depicted by block 712. As describedabove, the tristate devices instead of the buffers may be used to test amemory card.

FIG. 8 illustrates a high level flow chart which illustrates testing amemory controller using a prior art method in accordance with thepresent invention. The process for testing a memory controller starts asdepicted by block 800 and thereafter passes to block 802 whichillustrates testing of a memory controller using any of the prior artmethods such as Built In Self Test (BIST) or JTAG scan chain signatureverification. The process then terminates as illustrated by block 804.

It is important to note that while the present invention has beendescribed in the context of a fully functioning data processing system,those of ordinary skill in the art will appreciate that the processes ofthe present invention are capable of being distributed in the form of acomputer readable medium of instructions and a variety of forms and thatthe present invention applies equally regardless of the particular typeof signal bearing media actually used to carry out the distribution.Examples of computer readable media include recordable-type media, suchas a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs, andtransmission-type media, such as digital and analog communicationslinks, wired or wireless communications links using transmission forms,such as, for example, radio frequency and light wave transmissions. Thecomputer readable media may take the form of coded formats that aredecoded for actual use in a particular data processing system.

The description of the present invention has been presented for purposesof illustration and description, and is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the art. Theembodiment was chosen and described in order to best explain theprinciples of the invention, the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A method in a data processing system for isolating a defect in amemory system to a particular memory system component, said methodcomprising the steps of: said memory system including a plurality ofcomponents, said plurality of components including a physical memorymodule coupled to a memory card, said memory card, and a memorycontroller for controlling said memory card; and testing each one ofsaid plurality of components separately to identify a defective one ofsaid plurality of components.
 2. The method according to claim 1,further comprising the steps of: testing said physical memory module; inresponse to said physical memory module passing said test, testing saidmemory card; and in response to said memory card passing said test,testing said memory controller.
 3. The method according to claim 2,further comprising the steps of: said memory card including a buffer;and wherein said step of testing said memory card includes: treatingsaid buffer as a virtual memory module; and testing said memory cardutilizing said virtual memory module.
 4. The method according to claim2, further comprising the steps of: said memory card including a buffer;and wherein said step of testing said physical memory module includes:treating said buffer as a virtual memory controller; and testing saidphysical memory module utilizing said virtual memory controller.
 5. Themethod according to claim 2, further comprising the steps of: saidmemory card including a buffer; and wherein said step of testing saidmemory card includes: treating said buffer as a virtual memory module;and testing said memory card utilizing said buffer by writing a datapattern to said memory card to be stored in said virtual memory module;said step of testing said memory card including: storing said datapattern in said virtual memory module; reading a data pattern from saidvirtual memory; comparing said data pattern written to said virtualmemory module to said data pattern read from said virtual memory module;determining that said memory card passed said test in response to saiddata pattern written to said virtual memory module being the same assaid data pattern read from said virtual memory module; and determiningthat said memory card failed said test in response to said data patternwritten to said virtual memory module being different from said datapattern read from said virtual memory module.
 6. The method according toclaim 3, further comprising the steps of: said memory card including aplurality of buffers; and assigning a unique identifier to each one ofsaid plurality of buffers for addressing said plurality of buffers. 7.The method according to claim 3, further comprising the steps of:coupling said buffer to a service processor; and testing, utilizing saidservice processor, said memory card.
 8. The method according to claim 7,further comprising the steps of: coupling said buffer to said serviceprocessor utilizing a JTAG bus.
 9. The method according to claim 2,further comprising the steps of: storing a data pattern in said memorycontroller; reading a data pattern from said memory controller;comparing said data pattern written to said memory controller to saiddata pattern read from said memory controller; determining that saidmemory controller passed said test in response to said data patternwritten to said memory controller being the same as said data patternread from said memory controller; and determining that said memorycontroller failed said test in response to said data pattern written tosaid memory controller being different from said data pattern read fromsaid memory controller.
 10. The method according to claim 9, furthercomprising the steps of: coupling said memory controller to a serviceprocessor.
 11. The method according to claim 9, further comprising thesteps of: coupling said memory controller to a service processorutilizing a JTAG bus.
 12. The method according to claim 2, furthercomprising the steps of: said memory card including a tristate device;and wherein said step of testing said memory card includes: treatingsaid tristate device as a virtual memory module; and testing said memorycard utilizing said virtual memory module.
 13. The method according toclaim 12, further comprising the steps of: said memory card including atristate device; and wherein said step of testing said memory cardincludes: treating said tristate device as a virtual memory module; andtesting said memory card utilizing said virtual memory module by writinga data pattern to said memory card; said step of testing said memorycard including: storing said data pattern in said tristate device;reading a data pattern from said tristate device; comparing said datapattern written to said tristate device to said data pattern read fromsaid tristate device; determining that said memory card passed said testin response to said data pattern written to said tristate device beingthe same as said data pattern read from said tristate device; anddetermining that said memory card failed said test in response to saiddata pattern written to said tristate device being different from saiddata pattern read from said tristate device.
 14. A data processingsystem for isolating a defect in a memory system to a particular memorysystem component, said system comprising: said memory system including aplurality of components, said plurality of components including aphysical memory module coupled to a memory card, said memory card, and amemory controller for controlling said memory card; and logic that testseach one of said plurality of components separately to identify adefective one of said plurality of components.
 15. The system accordingto claim 14, further comprising: logic that tests said physical memorymodule; in response to said physical memory module passing said test,logic that tests said memory card; and in response to said memory cardpassing said test, logic that tests said memory controller.
 16. Thesystem according to claim 15, further comprising: said memory cardincluding a buffer; and wherein said logic that tests said memory cardincludes: said buffer acting as a virtual memory module; and logic thattests said memory card utilizing said virtual memory module.
 17. Thesystem according to claim 15, further comprising: said memory cardincluding a buffer; and wherein said logic that tests said memory cardincludes: said buffer acting as a virtual memory module; and logic thattests said memory card utilizing said buffer by writing a data patternto said memory card to be stored in said virtual memory module; saidlogic that tests said memory card including: storing means for storingsaid data pattern in said virtual memory module; reading means forreading a data pattern from said virtual memory; comparing means forcomparing said data pattern written to said virtual memory module tosaid data pattern read from said virtual memory module; determiningmeans for determining that said memory card passed said test in responseto said data pattern written to said virtual memory module being thesame as said data pattern read from said virtual memory module; anddetermining means for determining that said memory card failed said testin response to said data pattern written to said virtual memory modulebeing different from said data pattern read from said virtual memorymodule.
 18. The system according to claim 16, further comprising: saidmemory card including a plurality of buffers; and assigning means forassigning a unique identifier to each one of said plurality of buffersfor addressing said plurality of buffers.
 19. The system according toclaim 16, further comprising: said buffer being coupled to a serviceprocessor; and said service processor for testing said memory card. 20.The system according to claim 19, further comprising: said buffer beingcoupled to said service processor utilizing a JTAG bus.
 21. The systemaccording to claim 15, further comprising: storing means for storing adata pattern in said memory controller; reading means for reading a datapattern from said memory controller; comparing means for comparing saiddata pattern written to said memory controller to said data pattern readfrom said memory controller; determining means for determining that saidmemory controller passed said test in response to said data patternwritten to said memory controller being the same as said data patternread from said memory controller; and determining means for determiningthat said memory controller failed said test in response to said datapattern written to said memory controller being different from said datapattern read from said memory controller.
 22. The system according toclaim 21, further comprising: said memory controller being coupled to aservice processor utilizing a JTAG bus.
 23. The system according toclaim 15, further comprising: said memory card including a tristatedevice; and wherein said logic that tests said memory card includes:said tristate device acting as a virtual memory module; and logic thattests said memory card utilizing said virtual memory module.
 24. Thesystem according to claim 15, further comprising: said memory cardincluding a buffer; and wherein said logic that tests said physicalmemory module includes: said buffer acting as a virtual memorycontroller; and logic that tests said physical memory module utilizingsaid buffer acting as said virtual memory controller.
 25. A computerprogram product in a data processing system for isolating a defect in amemory system to a particular memory system component, said productcomprising: said memory system including a plurality of components, saidplurality of components including a physical memory module coupled to amemory card, said memory card, and a memory controller for controllingsaid memory card; and instruction means for testing each one of saidplurality of components separately to identify a defective one of saidplurality of components.
 26. The product according to claim 25, furthercomprising: instruction means for testing said physical memory module;in response to said physical memory module passing said test,instruction means for testing said memory card; and in response to saidmemory card passing said test, instruction means for testing said memorycontroller.
 27. The product according to claim 26, further comprising:said memory card including a buffer; and wherein said instruction meansfor testing said memory card includes: instruction means for treatingsaid buffer as a virtual memory module; and instruction means fortesting said memory card utilizing said virtual memory module.